1. Technical Field
This application is based upon and claims the benefit of the priority of Japanese patent application No. 2007-192026 filed on Jul. 24, 2007, the disclosure of which is incorporated herein in its entirety by reference thereto.
This invention relates to a semiconductor device in which a semiconductor chip is embedded in an insulating layer consisting of a resin or the like, and to a method of manufacturing this semiconductor device. More particularly, the invention relates to a high-yield semiconductor device exhibiting superior reliability, and to a method of manufacturing this device.
2. Description of the Related Art
Semiconductor devices that have become the focus of attention in recent years include a semiconductor device referred to as an “embedded-chip substrate”, in which a semiconductor chip such as a diced LSI chip has been embedded in a resin substrate, or a semiconductor device having an insulating resin layer and a wiring layer formed directly on a semiconductor chip without the intermediary of a solder bump or like. In such semiconductor devices as the embedded-chip substrate, it is necessary to electrically connect external connection pads for the chip and external wiring by forming vias after the chip is embedded in the insulating material.
A photosensitive resin in which vias can be formed by exposure and development is capable of being used as the insulating material used in the embedded-chip substrate. However, since photosensitive resin generally has little mechanical strength, a semiconductor device that uses photosensitive resin as the insulating material often involves problems in terms of reliability. For this reason, non-photoconductive resin often is used as the insulating material of the semiconductor device. Non-photoconductive resin exhibits superior reliability owing to its large mechanical strength and, since it is used widely in printed circuit boards and the like, is additionally advantageous in that it can be produced in large quantity and at a low cost.
In a case where non-photoconductive resin is used as the insulating layer of a semiconductor device that internally incorporates a semiconductor chip, formation of vias by laser irradiation generally is used because the vias cannot be formed by exposure and development. In a semiconductor device internally incorporating a semiconductor chip, a chip that has been diced from a wafer is mounted on a supporting substrate or the like. Then, in order to form vias, laser vias are formed in the entirety of the substrate, on which the chip is mounted, using a common positioning mark. Consequently, it is difficult to form highly precise laser vias owing to error in chip-mounting accuracy. Accordingly, in order to assure a high accuracy in positions of vias by so arranging it that there is no chip mounting error, it is preferred that laser vias be formed using as a reference a positioning mark corresponding to each individual chip.
In relation to a technique for forming laser vias using a positioning mark as a reference, Patent Document 1 (see FIG. 8) discloses forming a positioning mark 131 on a core substrate 130 using a positioning mark 123 of an IC chip 120 as a reference and forming vias (via holes) 160 in conformity with the positioning mark 131. As a result, the vias 160 can be formed accurately on pads 124 of the IC chip 120 and the pads 124 and via holes 160 can be connected reliably.
[Patent Document 1] Japanese Patent Kokai Publication No. 2001-332863 (FIG. 6)